1. Technical Field of the Invention
The present invention relates generally to a synchronization adder circuit which may be employed in a receiver of a digital communication system to synchronously add the power of sampled received signals, and more particularly to such a synchronization adder circuit having an improved compact structure.
2. Background Art
In a known digital communication system, a receiver samples signal levels of a received signal at time intervals corresponding to transmission intervals at which a transmitter transmits symbols (1, 0), and compares them with a threshold value to reproduce original symbols.
For transmission of digital data in a narrow band, the Nyquist characteristic is generally used. The same filter having the root Nyquist properties is usually employed both in transmitter and receiver. In such digital transmission, the sampling timing where a symbol is sampled from a received signal can be determined based on a maximum point of the envelope of the received signal unless a limiter amplifier is used as a receiver amplifier.
The receiver digitizes the received signal at a sampling frequency that is an integral multiple (N) of a symbol-clock frequency, synchronously adds a square mean of samples at Nth sample points in time, and then identifies the samples at the Nth sample points having a maximum square means as indicating transmitted symbols.
In order to enhance the communication efficiency, known digital communication usually uses a plurality of subcarriers whose carrier frequencies are gradually shifted from the center frequency for transmitting a great deal of data. It is possible to improve the detection ability of symbol-timing (i.e., the symbol-clock frequency) by using the sum of the envelopes of the subcarriers.
FIG. 5 shows a conventional synchronization adder circuit which includes generally A/D converters 21 and 22, frequency converters 31, 32, 33, and 34, waveform-shaping filters 51, 52, 53, 54, 55, 56, 57, and 58, square circuits 71, 72, 73, 74, 75, 76, 77, and 78, an adder 81, an adder circuit 82, a memory 83, and a discrimination point detecting circuit 84.
The A/D converter 21 digitizes the same phase component 11 (I signal) of a received signal on each subcarrier at a sampling frequency of N times a symbol-clock frequency. The A/D converter 22 digitizes at the same sampling frequency an orthogonal component 12 (Q signal) of the received signal on each subcarrier. The frequency convert 31 to 34 frequency-convert the digital signals 23 and 24 on each subcarrier outputted from the A/D converters 21 and 22 to have their central frequencies agree with one another. The waveform-shaping filters 51 to 58 waveform-shape with the same filtering properties the I and Q signals on each subcarrier whose center frequencies have agreed with each other. The square circuits 71 to 78 square the waveform-shaped signals 61 to 68, respectively. The adder 81 forms the sum of outputs from the square circuits 71 to 78. The adder circuit 82 adds an output value from the adder 81 to the sum of the outputs from the square circuits 71 to 78 derived at a previous corresponding sampling point which, in turn, is stored in a given location, one for each sampling point, of the memory 83.
Note that the synchronization adder circuit shown in FIG. 4 receives data transmitted on four subcarriers and an A/D conversion is made seven times (N=7) per sampling cycle.
In operation, data transmitted on four subcarriers is separated by means of orthogonal detection into the I and Q signals which are, in turn, inputted into the A/D converters 21 and 22 wherein they are digitized at a sampling frequency of seven times the symbol-clock frequency.
Subsequently, the digitized I and Q signals are inputted into the frequency converters 31 to 34. The four subcarriers have carrier frequencies which are shifted from the center frequency by -3.DELTA..omega., -.DELTA..omega., .DELTA..omega., and 3.DELTA..omega., respectively. Each frequency converter 31 to 34 is thus arranged to frequency-converts the I and Q signals to have the center frequencies thereof coincide with one another (0 Hz) for taking a corresponding subcarrier out of the I and Q signals. FIGS. 6(a) and 6(b) show the frequency conversion in the frequency converters. For example, a central frequency offset by .DELTA..omega., as shown in FIG. 6(a), is shifted by +.DELTA..omega. into a central frequency zero shown in FIG. 6(b).
The signals 41 to 48 processed by the frequency converters 31 to 34 are inputted into the waveform-shaping circuits 51 to 58. These waveform-shaping circuits are designed to extract, as shown in FIG. 6(c), a signal in a frequency range defined by the same width across the center frequency.
The outputs from the waveform-shaping circuits 51 to 58 are squared in the square circuits 71 to 78 to derive the envelopes thereof. The outputs of the square circuits 71 to 78 are then added in the adder 81 to form the sum of the envelopes of the four subcarriers.
A value provided by the adder 81 is added in the adder circuit 82 to a value already stored in a corresponding memory location of the memory 83. The memory 83 has seven memory locations each storing a total value of samples derived at corresponding sampling points in past sapling cycles. For example, when an instantaneous value of the adder 81 is derived at the second sampling point, the sum of samples obtained at the second sampling points in previous sampling cycles is first read out of the second memory location of the memory 83 and then is added to the value currently derived by the adder 81 which, in turn, is stored in the second memory location of the memory 83 again.
The discrimination point detecting circuit 84 detects in the memory 83 a maximum total value of the samples extracted at individual sampling points for given sapling cycles, and identifies the samples having the maximum total value as optimum samples for reproduction of symbols.
The above prior art synchronization adder circuit, however, encounters the drawback in that in order to derive the envelopes of four subcarriers, it is necessary to perform frequency-conversion four times and filtering process eight times, as discussed above. In other words, the frequency conversions of a number corresponding to the number of subcarriers and the filtering processes of twice the number of subcarriers are required. This results in bulky hardware of the circuit. Alternatively, in the case where the above variety of operations are executed in software, it becomes difficult to perform such operations in real time.